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| mos integrated circuit pd48288118 288m-bit low latency dram separate i/o document no. m18814ej4v0ds00 date published january 2008 printed in japan data sheet t he information in this document is subject to change without notice. before using this document, pleas e c onfirm that this is the latest version. n ot all products and/or types are available in every country. please check with an nec electronic s s ales representative for availability and additional information. 2006, 2009 description the pd48288118 is a 16,777,216 word by 18 bit synchronous double data rate low latency ram fabricated with advanced cmos technology using one-transistor memory cell. the pd48288118 integrates unique synchronous peripheral circuitr y and a burst counter. all input registers controlled by an input clock pair (ck and ck#) are latc hed on the positive edge of ck and ck#. these products are suitable for application which require sync hronous operation, high speed, low voltage, high density and wide bit configuration. specification ? density: 288m bit ? organization - separate i/o: 2m words x 18 bits x 8 banks ? operating frequency: 400 / 300 / 200 mhz ? interface: hstl i/o ? package: 144-pin tape fbga - package size: 18.5 x 11 - leaded and lead free ? power supply - 2.5 v v ext - 1.8 v v dd - 1.5 v or 1.8 v v dd q ? refresh command - auto refresh - 8192 cycle / 32 ms for each bank - 64k cycle / 32 ms for total ? operating case temperature : tc = 0 to 95c features ? sram-type interface ? double-data-rate architecture ? pll circuitry ? cycle time: 2.5 ns @ t rc = 20 ns 3.3 ns @ t rc = 20 ns 5.0 ns @ t rc = 20 ns ? non-multiplexed addresses ? multiplexing option is available. ? data mask for write commands ? differential input clocks (ck and ck#) ? differential input data clocks (dk and dk#) ? data valid signal (qvld) ? programmable burst length: 2 / 4 / 8 ? user programmable impedance output (25 - 60 ) ? jtag boundary scan
2 data sheet m18814ej4v0ds pd48288118 ordering information part number cycle clock random organization core supply core supply output supply package time frequency cycle (word x bit) voltage voltage voltage (v ext ) (v dd ) (v dd q) ns mhz ns v v v pd48288118ff-e25-dw1 2.5 400 20 16m x 18 bit 2.5 + 0.13 1.8 0.1 1.8 0.1 144-pin pd48288118ff-e33-dw1 3.3 300 20 2.5 ? 0.12 tape fbga pd48288118ff-e50-dw1 5.0 200 20 (18.5 x 11) pd48288118ff-ef25-dw1 2.5 400 20 1.5 0.1 pd48288118ff-ef33-dw1 3.3 300 20 pd48288118ff-ef50-dw1 5.0 200 20 pd48288118ff-e25-dw1-a 2.5 400 20 16m x 18 bit 2.5 + 0.13 1.8 0.1 1.8 0.1 144-pin pd48288118ff-e33-dw1-a 3.3 300 20 2.5 ? 0.12 tape fbga pd48288118ff-e50-dw1-a 5.0 200 20 (18.5 x 11) pd48288118ff-ef25-dw1-a 2.5 400 20 1.5 0.1 pd48288118ff-ef33-dw1-a 3.3 300 20 lead-free pd48288118ff-ef50-dw1-a 5.0 200 20 remark products with ?a at the end of pa rt number are lead-free products. 3 data sheet m18814ej4v0ds pd48288118 pin configurations # indicates active low signal. 144-pin tape fbga (18.5 x 11) (top view) [separate i/o x18] 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd d4 q4 v ss q v ss qq0 d0 v dd c v tt d5 q5 v dd q v dd qq1 d1 v tt d note 1 (a22) d6 q6 v ss q v ss q qk0# qk0 v ss e note 1 (a21) d7 q7 v dd q v dd qq2 d2 note 1 (a20) f a5 d8 q8 v ss q v ss qq3 d3 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h ba2 a9 v ss v ss v ss v ss a4 a3 j note 2 nf note 2 nf v dd v dd v dd v dd ba0 ck k dk dk# v dd v dd v dd v dd ba1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 d14 q14 v ss q v ss q q9 d9 a19 p a15 d15 q15 v dd q v dd q q10 d10 dm r v ss qk1 qk1# v ss q v ss q q11 d11 v ss t v tt d16 q16 v dd q v dd q q12 d12 v tt u v dd d17 q17 v ss q v ss q q13 d13 v dd v v ref zq v ext v ss v ss v ext tdo tdi notes 1. reserved for future use. this signal is internally c onnected and has parasitic c haracteristics of an address input signal. this may optionally be connected to v ss , or left open. 2. no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to v ss , or left open. ck, ck# : input clock zq : output impedance matching cs# : chip select tms : ieee 1149.1 test input we# : write command tdi : ieee 1149.1 test input ref# : refresh command tck : ieee 1149.1 clock input a0?a19 : address inputs tdo : ieee 1149.1 test output a20?a22 : reserved for the future v ref : hstl input reference input ba0?ba2 : bank address input v ext : power supply d0?d17 : data input v dd : power supply q0?q17 : data output v dd q : dq power supply dk, dk# : input data clock v ss : ground dm : input data mask v ss q : dq ground qk0?qk1, qk0#?qk1# : output data clock v tt : power supply qvld : data valid nf : no function 4 data sheet m18814ej4v0ds pd48288118 pin identification (1/2) symbol type description ck, ck# input clock inputs: ck and ck# are differential clock inputs. this i nput clock pair registers address and control inputs on the rising edge of ck. ck# is ideally 180 degrees out of phase with ck. cs# input chip select cs# enables the commands when cs# is low and disables them when cs# is high. when the command is disabled, new commands are ignor ed, but internal operations continue. we#, ref# input write command pin, refresh command pin: we#, ref# are sampled at the positive edge of ck , we#, and ref# define (together with cs#) the command to be executed. a0?a19 input address inputs: a0?a19 define the row and column addresses for read and write operations. during a mode register set, the address inputs define the regi ster settings. they are sampled at the rising edge of ck. a20?a22 input reserved for future use: these signals should be tied to v ss or leave open. ba0?ba2 input bank address inputs; select to which internal bank a command is being applied. d0?d17 input data input: the d signals form the 18-bit input data bus. du ring write commands, the data is referenced to both edges of dk. q0?q17 output data output: the q signals form the 18-bit output data bus. du ring read commands, the data is referenced to both edges of qk. qkx, qkx# output output data clocks: qkx and qkx# are opposite polarity, output data clocks. they are always free running and edge- aligned with data output from the pd48288118. qkx# is ideally 180 degrees out of phase with qkx. qk0 and qk0# are aligned with q0?q8. qk1 and qk1# are aligned with q9?q17. dk, dk# input input data clock; dk and dk# are the differential input data clocks. a ll input data is referenced to both edges of dk. dk# is ideally 180 degrees out of phase with dk. d0?d17 are referenced to dk and dk#. dm input input data mask; the dm signal is the input mask signal for write data. input data is masked when dm is sampled high along with the write input data. dm is sa mpled on both edges of dk. the signal should be v ss if not used. qvld output data valid; the qvld indicates valid output data. qvld is edge-aligned with qkx and qkx#. 5 data sheet m18814ej4v0ds pd48288118 (2/2) symbol type description zq input /output external impedance [25 ? 60 ]; this signal is used to tune the device output s to the system data bus impedance. q output impedance is set to 0.2 x rq, where rq is a resistor from this signal to v ss . connecting zq to v ss invokes the minimum impedance mode. connecting zq to v dd q invokes the maximum impedance mode. refer to figure 2-5. mode register bit map to activate this function. tms , tdi input jtag function pins: ieee 1149.1 test inputs: these balls may be left as no connects if the jtag function is not used in the circuit tck input jtag function pin; ieee 1149.1 clock input: this ball must be tied to v ss if the jtag function is not used in the circuit. tdo output jtag function pin; ieee 1149.1 test output: jtag output. this ball may be left as no connect if jtag function is not used. v ref input input reference voltage; nominally v dd q/2. provides a reference voltage for the input buffers. v ext supply power supply; 2.5 v nominal. see recommended dc operating conditions for range. v dd supply power supply; 1.8 v nominal. see recommended dc operating conditions for range. v dd q supply dq power supply; nominally, 1.5 v or 1.8 v. isolated on the device for improved noise immunity. see recommended dc operating conditions for range. v ss supply ground v ss q supply dq ground; isolated on the device for improved noise immunity. v tt supply power supply; isolated termination supply. nominally, v dd q/2. see recommended dc operating conditions for range. nf no function; these balls may be connected to v ss . 6 data sheet m18814ej4v0ds pd48288118 block diagram 16m x 18 a0-a19 note 1, note 2 , b0, b1, b2 column address buffer column address counter refresh counter row decoder memory array bank 1 column decoder sense amp and data bus row address buffer row decoder memory array bank 0 column decoder sense amp and data bus row decoder memory array bank 2 column decoder sense amp and data bus row decoder memory array bank 3 column decoder sense amp and data bus row decoder memory array bank 5 column decoder sense amp and data bus row decoder memory array bank 4 column decoder sense amp and data bus row decoder memory array bank 6 column decoder sense amp and data bus row decoder memory array bank 7 column decoder ck ck# dk dk# we# cs# ref# dm v ref sense amp and data bus output data valid qvld output data clock qk0-qk1, qk0#-qk1# output buffers control logic and timing generator input buffers q0-q17 d0-d17 notes 1. when the bl=8 setting is used, a18 and a19 are ?don?t care?. 2. when the bl=4 setting is used, a19 is ?don?t care?. 7 data sheet m18814ej4v0ds pd48288118 contents 1. electrical sp ecifications ................................................................................................... ........................ 8 2. operation................................................................................................................... ............................... 16 2.1 command op eration .......................................................................................................... ............................... 16 2.2 description of commands .................................................................................................... ............................ 16 2.3 initia lization ............................................................................................................. ........................................... 17 2.4 power-on sequence .......................................................................................................... ................................ 18 2.5 programmable impeda nce output buffer....................................................................................... ................. 18 2.6 pll reset .................................................................................................................. ......................................... 18 2.7 clock input ................................................................................................................ ......................................... 18 2.8 mode register set comma nd (mrs)............................................................................................ .................... 20 2.9 read & write configuration (n on multiplexed address mode) .................................................................. .... 21 2.10 write operat ion (write) ................................................................................................... .............................. 22 2.11 read oper ation (read)..................................................................................................... .............................. 25 2.12 refresh operation: au to refresh co mmand (aref)............................................................................ .. 30 2.13 on-die termina tion........................................................................................................ .................................. 31 2.14 operation with mu ltiplexed address........................................................................................ ...................... 33 2.15 address mapping in multipl exed mode....................................................................................... ................... 35 2.16 read& write configuration in multiplexed address mode ..................................................................... ...... 36 2.17 refresh command in mu ltiplexed a ddress m ode............................................................................... .......... 36 3. jtag spec ificat ion.......................................................................................................... ........................ 38 4. package drawing ............................................................................................................. ........................ 45 5. recommended sold ering condition ............................................................................................. ........ 46 6. revision history ............................................................................................................ .......................... 47 8 data sheet m18814ej4v0ds pd48288118 1. electrical specifications absolute maximum ratings parameter symbol conditions rating unit note supply voltage v ext ?0.3 to +2.8 v supply voltage v dd ?0.3 to +2.1 v output supply voltage, v dd q 1.8 v nominal ?0.3 to +2.1 v 1 input voltage, input / output voltage 1.5 v nominal ?0.3 to +1.975 v 1 input / output voltage v ih / v il 1.8 v nominal ?0.3 to +2.1 v 1 1.5 v nominal ?0.3 to +1.975 v 1 junction temperature t j max. 110 c storage temperature t stg ?55 to +125 c note 1. the pd48288118ff-e support 1.8 v v dd q nominal. the pd48288118ff-ef support 1.5 v v dd q nominal. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this sp ecification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions 0c t c 95c; 1.7 v v dd 1.9 v, unless otherwise noted parameter symbol conditions min. typ. max. unit note supply voltage v ext 2.38 2.5 2.63 v 1 supply voltage v dd 1.7 1.8 1.9 v 1 output supply voltage v dd q 1.7 1.8 1.9 v 1, 2, 3 1.4 1.5 1.6 v 1, 3 reference voltage v ref 0.49 x v dd q 0.5 x v dd q 0.51 x v dd q v 1, 4, 5 termination voltage v tt 0.95 x v ref v ref 1.05 x v ref v 1, 6 input high voltage v ih (dc) v ref + 0.1 v 1 input low voltage v il (dc) v ref ? 0.1 v 1 notes 1. all voltage referenced to v ss (gnd). 2. during normal operation, v dd q must not exceed v dd . 3. the pd48288118ff-e support 1.8 v v dd q nominal. the pd48288118ff-ef support 1.5 v v dd q nominal. 4. typically the value of v ref is expect to be 0.5 x v dd q of the transmitting device. v ref is expected to track variations in v dd q. 5. peak-to-peak ac noise on v ref must not exceed 2% v ref (dc). 6. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 9 data sheet m18814ej4v0ds pd48288118 dc characteristics 0c t c 95c; 1.7 v v dd 1.9 v, unless otherwise noted parameter symbol test condition min. max. unit note input leakage current i li ?5 +5 a 1,2 output leakage current i lo ?5 +5 a 1,2 reference voltage current i ref ?5 +5 a 1,2 output high current i oh v oh = v dd q/2 (v dd q/2) / (1.15 x rq/5) (v dd q/2) / (0.85 x rq/5) ma 3,4 output low current i ol v ol = v dd q/2 (v dd q/2) / (1.15 x rq/5) (v dd q/2) / (0.85 x rq/5) ma 3,4 notes 1. outputs are impedance-controlled. | i oh | = (v dd q/2)/(rq/5) for values of 125 rq 300 . 2. outputs are impedance-controlled. i ol = (v dd q/2)/(rq/5) for values of 125 rq 300 . 3. i oh and i ol are defined as absolute values and are measured at v dd q/2. i oh flows from the device, i ol flows into the device. 4. if mrs bit a8 is 0, use rq = 250 in the equation in lieu of presence of an external impedance matched resistor. capacitance (t a = 25 c, f = 1mhz) parameter symbol test conditions min. max. unit address / control input capacitance c in v in = 0 v 1.5 2.5 pf i/o, output, other capacitance c i/o v i/o = 0 v 3.5 5.0 pf (d, q, dm, qk, qvld) clock input capacitance c clk v clk = 0 v 2.0 3.0 pf jtag pins c j v j = 0 v 2.0 5.0 pf remark these parameters are periodically sampled and not 100% tested. ca pacitance is not tested on zq pin. recommended ac operating conditions 0c t c 95c; 1.7 v v dd 1.9 v, unless otherwise noted parameter symbol conditions min. max. unit note input high voltage v ih (ac) v ref + 0.2 v 1 input low voltage v il (ac) v ref ? 0.2 v 1 note 1. overshoot: v ih (ac) v dd q + 0.7 v for t t ck /2 undershoot: v il (ac) ? 0.5 v for t t ck /2 control input signals may not have pulse widths less than t ckh (min.) or operate at cycle rates less than t ck (min.). 10 data sheet m18814ej4v0ds pd48288118 dc characteristics i dd / i sb operating conditions parameter symbol test condition max. unit ?e25, ?e33, ?e50, ?ef25 ?ef33 ?ef50 standby current i sb1 t ck = idle v dd 48 48 48 ma all banks idle, no inputs toggling v ext 26 26 26 active standby i sb2 cs# = high, no commands, half bank / address / v dd 288 233 189 ma current data change once every four clock cycles v ext 26 26 26 operating current i dd1 bl=2, sequential bank access, bank transitions v dd 365 325 265 ma once every t rc , half address transitions once every t rc , read followed by write sequence, v ext 41 36 36 continuous data during write commands. operating current i dd2 bl=4, sequential bank access, bank transitions v dd 360 340 270 ma once every t rc , half address transitions once every t rc , read followed by write sequence, v ext 48 42 42 continuous data during write commands. operating current i dd3 bl=8, sequential bank access, bank transitions v dd 400 360 ? ma once every t rc , half address transitions once every t rc , read followed by write sequence, v ext 55 48 ? continuous data during write commands. burst refresh i ref1 eight bank cyclic refresh, continuous v dd 650 540 400 ma current address/data, command bus remains in refresh v ext 133 111 105 for all banks disturbed i ref2 single bank refresh, sequential bank access, v dd 310 260 210 ma refresh current half addre ss transitions once every t rc , v ext 48 42 42 continuous data operating burst i dd2w bl=2, cyclic bank access, half of address bits v dd 970 820 550 ma write current change every clock cycle, continuous data, v ext 100 90 69 measurement is taken dur ing continuous write operating burst i dd4w bl=4, cyclic bank access, half of address bits v dd 690 560 410 ma write current change every two clocks, continuous data, v ext 88 77 63 measurement is taken dur ing continuous write operating burst i dd8w bl=8, cyclic bank access, half of address bits v dd 600 450 ? ma write current change every four clocks, continuous data, v ext 60 51 ? measurement is taken dur ing continuous write operating burst i dd2r bl=2, cyclic bank access, half of address bits v dd 970 840 560 ma read current change every clock cycle, measurement is taken v ext 100 90 69 during continuous read operating burst i dd4r bl=4, cyclic bank access, half of address bits v dd 720 580 420 ma read current change every two cl ocks, measurement is taken v ext 88 77 63 during continuous read operating burst i dd8r bl=8, cyclic bank access, half of address bits v dd 550 450 ? ma read current change every four cl ocks, measurement is taken v ext 60 51 ? during continuous read 11 data sheet m18814ej4v0ds pd48288118 remarks 1. i dd specifications are tested after the device is properly initialized. 0c t c 95c; 1.7 v v dd 1.9 v, 2.38 v v ext 2.63 v, 1.7 v v dd q 1.9 v (?e), 1.4 v v dd q 1.6 v (?ef), v ref = v dd q/2 2. t ck = t dk = min., t rc = min. 3. input slew rate is specified in recommended dc operating conditions and recommended ac operating conditions . 4. i dd parameters are specifi ed with odt disabled. 5. continuous data is defined as half the d or q signa ls changing between high and low every half clock cycles (twice per clock). 6. continuous address is defined as half the addre ss signals between high and low every clock cycles (once per clock). 7. sequential bank access is defined as the bank address incrementing by one ever t rc . 8. cyclic bank access is defined as the bank addre ss incrementing by one for each command access. for bl=4 this is every other clock. 9. cs# is high unless a read, write, aref, or mrs command is registered. cs# never transitions more than per clock cycle. 12 data sheet m18814ej4v0ds pd48288118 ac characteristics ac test conditions input waveform v ih ( ac ) min. v il ( ac ) max. rise time: 2 v/ns fall time: 2 v/ns v dd q v ss output waveform v dd q / 2 v dd q / 2 test points output load condition 10pf q 50 v tt test point 13 data sheet m18814ej4v0ds pd48288118 ac characteristics 14 data sheet m18814ej4v0ds pd48288118 ac characteristics 15 data sheet m18814ej4v0ds pd48288118 figure 1-1. clock / input data clock command / address timings ck# ck t ck t ckdk t ckdk t dk t dkh t dkl t as t ah t ckh t ckl command, address dk# dk valid valid valid dont care temperature and thermal impedance temperature limits parameter symbol min. max. unit note reliability junction temperature t j 0 +110 c 1 operating junction temperature t j 0 +100 c 2 operating case temperature t c 0 +95 c 3 notes 1. temperatures greater than 110c may cause permanent damage to the device. this is a stress rating only and functional operation of the device at or above this is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability of the part. 2. junction temperature depends upon cycle time, loading, ambient temperature, and airflow. 3. max operating case temperature; t c is measured in the center of the package. device functionality is not guaranteed if the device exceeds maximum t c during operation. thermal impedance substrate ball ja ( c /w) jb jc air flow = 0 m/s air flow = 1 m/s air flow = 2 m/s ( c /w) ( c /w) 4 - layer lead 32.4 26.8 24.6 23.0 1.8 8 - layer lead 26.5 22.3 20.8 16.8 1.8 4 - layer lead free 32.1 26.6 24.4 22.7 1.8 8 - layer lead free 26.3 22.1 20.6 16.6 1.8 16 data sheet m18814ej4v0ds pd48288118 2. operation 2.1 command operation according to the functional signal description, the follo wing command sequences are possi ble. all input states or sequences not shown are illegal or reserved. all command and address inputs must meet setup and hold times around the rising edge of ck. table 2-1. address widths at different burst lengths burst length configuration bl=2 a0?a19 bl=4 a0?a18 bl=8 a0?a17 table 2-2. command table operation code cs# we# ref# a0?a19 ba0?ba2 notes device deselect / no operation desel / nop h x x x x mrs: mode register set mrs l l l opcode x 1 read read l h h a ba 2 write write l l h a ba 2 auto refresh aref l h l x ba notes 1. only a0?a17 are used for the mrs command. 2. see table 2-1. remark x = ?don?t care?, h = logic high, l = logic low, a = valid address, ba = valid bank address 2.2 description of commands desel / nop note1 the nop command is used to perform a no operation to the pd48288118, which essentially deselects the chip. use the nop command to prevent unwanted comm ands from being registered during idle or wait states. operations already in progress are not affected. out put values depend on command history. mrs the mode register is set via the address inputs a0?a17. see figure 2-5. mode register bit map for further information. the mrs command can only be issued when all banks are idle and no bursts are in progress. read the read command is used to initiate a burst read acce ss to a bank. the value on the ba0?ba2 inputs selects the bank, and the address provided on inputs a0?a19 se lects the data location within the bank. write the write command is used to initiate a burst write a ccess to a bank. the value on the ba0?ba2 inputs selects the bank, and the address provided on inputs a 0?a19 selects the data location within the bank. input data appearing on the d is written to the memory array subject to the dm input logi c level appearing coincident with the data. if the dm signal is registered low, the corresponding data will be writt en to memory. if the dm signal is registered high, the corresponding data inputs will be ignored (i.e., this part of the data word will not be written). 17 data sheet m18814ej4v0ds pd48288118 aref the aref is used during normal operation of the pd48288118 to refresh the memory content of a bank. the command is non-persistent, so it must be issued each time a refresh is required. the value on the ba0?ba2 inputs selects the bank. the refresh address is generated by an inter nal refresh controller, effectively making each address bit a ?don?t care? during the aref command. the pd48288118 requires 64k cycles at an average periodic interval of 0.49 s note2 (max.). to improve efficiency, eight aref commands (one for each bank) can be posted to pd48288118 at periodic intervals of 3.9 s note3 . within a period of 32ms, the entire memory must be refreshed. the delay between the aref command and a subsequent command to same bank must be at least t rc as continuous refresh. other re fresh strategies, such as burst refresh, are also possible. notes 1. when the chip is deselected, internal nop co mmands are generated and no commands are accepted. 2. actual refresh is 32 ms / 8k / 8 = 0.488 s. 3. actual refresh is 32 ms / 8k = 3.90 s. 2.3 initialization the pd48288118 must be powered up and initialized in a pr edefined manner. operationa l procedures other than those specified may result in undefined operations or permanent damage to the device. the fo llowing sequence is used for power-up: 1. apply power (v ext , v dd , v dd q, v ref , v tt ) and start clock as soon as the s upply voltages are stable. apply v dd and v ext before or at the same time as v dd q. apply v dd q before or at the same time as v ref and v tt . although there is no timing relation between v ext and v dd , the chip starts the power-up sequence only after both voltages are at their nominal levels. v dd q supply must not be applied before v dd supply. ck/ck# must meet v id(dc) prior to being applied. maintain all remaining balls in nop conditions. note no rule of apply power sequence is the design target. 2. maintain stable conditions for 200 s (min.). 3. issue three or more back-to-back and clock consecutive mrs commands: two dummies plus one valid mrs. it is recommended that the dummy mrs commands are the same value as the desired mrs. 4. t mrsc after valid mrs, an auto refresh command to all 8 banks must be issued and wait for 15 s with ck/ck# toggling in order to lock the pll prior to normal operation. 5. after t rc , the chip is ready for normal operation. 18 data sheet m18814ej4v0ds pd48288118 2.4 power-on sequence figure 2-1. power-up sequence v ext v dd v dd q v ref ck# ck command 200 s min. t mrsc t rc refresh all banks mrs mrs mrs rf0 rf1 rf7 ac address v tt nop nop nop don't care a 15 s aa note 1, 2 note 1, 2 note 2 notes 1. recommended all address pins held low during dummy mrs commands. 2. a10-a17 must be low. remark mrs: mrs command rfp : refresh bank p ac : any command 2.5 programmable impedance output buffer the pd48288118 is equipped with programmable impedance output buffers. this allows a user to match the driver impedance to the system. to adjust the impedance, an external precision resistor (rq) is connected between the zq ball and v ss . the value of the resistor must be five time s the desired impedance. for example, a 300 resistor is required for an output impedance of 60 . to ensure that output impedance is one fifth the value of rq (within 15 percent), the range of rq is 125 to 300 . output impedance updates may be required bec ause, over time, variations may occur in supply voltage and temperature. the device samples the value of rq. an impedance update is transparent to the system and does not affect device operation. all data sheet timi ng and current specifications are met during an update. 2.6 pll reset the pd48288118 utilizes internal phase-locked loops for maxi mum output, data valid windows. it can be placed into a stopped-clock state to minimize power with a modest restart time of 15 s. the clock (ck/ck#) must be toggled for 15 s in order to stabilize pll circuits for next read operation. 2.7 clock input table 2-3. clock input operation conditions parameter symbol conditions min. max. unit note clock input voltage level v in (dc) ck and ck# -0.3 v dd q + 0.3 v clock input differential voltage level v id (dc) ck and ck# 0.2 v dd q + 0.6 v 8 clock input differential voltage level v id (ac) ck and ck# 0.4 v dd q + 0.6 v 8 clock input crossing point voltage level v ix (ac) ck and ck# v dd q/2 - 0.15 v dd q/2 + 0.15 v 9 19 data sheet m18814ej4v0ds pd48288118 figure 2-2. clock input v in(dc) max. ck# v dd q/2 + 0.15 v dd q/2 v dd q/2 - 0.15 ck v in(dc) min. minimum clock level v ix(ac) max. v ix(ac) min. v id(dc) note11 v id(ac) note12 note 10 maximum clock level notes 1. dk and dk# have the same requirements as ck and ck#. 2. all voltages referenced to v ss . 3. tests for ac timing, idd and electrical ac a nd dc characteristics may be conducted at normal reference/supply voltage levels; but the related specifications and devi ce operations are tested for the full voltage range specified. 4. ac timing and idd tests may use a v il to v ih swing of up to 1.5 v in the test environment, but input timing is still referenced to v ref (or the crossing point for ck/ck#), and par ameters specifications are tested for the specified ac input levels under normal use conditions. t he minimum slew rate for the input signals used to test the device is 2v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the hstl standard (i.e. the receiver will effectively switch as a result of the signal cro ssing the ac input level, and will remain in that state as long as the signal does not ring back above[below] the dc input low[high] level). 6. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross. the input reference level for signal other than ck/ck# is v ref . 7. ck and ck# input slew rate must be >=2v/ns (>=4v/ns if measured differentially). 8. v id is the magnitude of the difference between t he input level on ck and input level on ck#. 9. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 10. ck and ck# must cross within the region. 11. ck and ck# must meet at least v id(dc) (min.) when static and centered around v dd q/2. 12. minimum peak-to-peak swing. 20 data sheet m18814ej4v0ds pd48288118 2.8 mode register set command (mrs) the mode register stores the data for controlling t he operating modes of the memory. it programs the pd48288118 configuration, bur st length, and i/o optio ns. during a mrs command, the addr ess inputs a0?a17 are sampled and stored in the mode register. t mrsc must be met before any command can be issued to the pd48288118. the mode register may be set at any time during device operati on. however, any pending operations are not guaranteed to successfully complete. since mrs is used for internal test mode entry, the designated bit at figure 2-5. mode register bit map and figure 2-27. mode register set command in multiplexed address mode should be set. figure 2-3. mode register set timing ck# ck command t mrsc mrs nop nop ac don?t care qvld qkx qkx# remark mrs : mrs command ac : any command figure 2-4. mode register set ck# ck we# ref# address cs# cod bank address don?t care remark cod: code to be loaded into the register. 21 data sheet m18814ej4v0ds pd48288118 figure 2-5. mode register bit map a2 a4 a5 a17-a10 a3 a1 a0 a6 a7 a3 0 1 bl 4 a4 0 1 8 note 2 0 0 1 1 reserved note 1 a9 a7 0 1 a8 a2 a1 a0 10 configuration configuration configuration 1 note 2 (default) reserved reserved reserved 1 note 2 not valid 2 (default) pll enabled pll reset pll reset burst length burst length pll reset address mux address mux pll reset (default) 2 3 reserved 10 11 01 01 00 00 1 1 0 0 1 0 1 0 11 impedance matching impedance matching a8 0 1 resistor external note 3 (default) a5 0 1 nonmultiplexed (default) address multiplexed address mux a9 0 1 enabled termination on-die termination disabled (default) on-die termination unused note 4 notes 1. bits a10-a17 must be set to all ?0?. a18-an are ?don?t care?. 2. bl=8 is not available for configuration 1. 3. 30% temperature variation. 4. within 15%. 2.9 read & write configuration (non multiplexed address mode) table 2-4 shows, for different operat ing frequencies, the different pd48288118 configurations that can be programmed into the mode register . the read and write latency (t rl and t wl ) values along with the row cycle times (t rc ) are shown in clock cycles as well as in nanoseconds. the shaded areas correspond to configurations that are not allowed. table 2-4. configuration table frequency symbol configuration unit 1 note 2 3 t rc 4 6 8 cycles t rl 4 6 8 cycles t wl 5 7 9 cycles 400mhz t rc 20.0 ns t rl 20.0 ns t wl 22.5 ns 300mhz t rc 20.0 26.7 ns t rl 20.0 26.7 ns t wl 23.3 30.0 ns 200mhz t rc 20.0 30.0 40.0 ns t rl 20.0 30.0 40.0 ns t wl 25.0 35.0 45.0 ns note bl=8 is not available for configuration 1. 22 data sheet m18814ej4v0ds pd48288118 2.10 write operation (write) write accesses are initiated with a write command, as shown in figure 2-6 . row and bank addresses are provided together with the write command. during write commands, data will be registered at both edges of dk according to the programmed burst length (bl). a write latency (wl) one cycle longer than the programmed read latency (rl + 1) is present, with the first valid data registered at the first rising dk edge wl cycles after the write command. any write burst may be followed by a subsequent read command. figure 2-10. write followed by read: bl=2, rl=4, wl=5, configuration 1 and figure 2-11. write followed by read: bl=4, rl=4, wl=5, configuration 1 illustrate the timing requirements for a write followed by a read for bursts of two and four, respectively. setup and hold times for incoming input data relative to the dk edges are specified as t ds and t dh . the input data is masked if the corresponding dm signal is high. the setup and hold times for data mask are also t ds and t dh . figure 2-6. write command ck# ck we# ref# cs# address a ba don?t care bank address remark a : address ba : bank address figure 2-7. basic write burst / dm timing d dm t dh t ds d0 d3 dk# dk t dh t ds t dh t ds don't care write latency data masked data masked ck# ck t ckdk d1 d2 23 data sheet m18814ej4v0ds pd48288118 figure 2-8. write burst basic sequence: bl=2, rl=4, wl=5, configuration 1 ck# ck command 012345678 address wl = 5 d wr a ba1 a ba2 a ba3 a ba0 a ba4 a ba5 a ba6 a ba7 wr wr wr wr wr wr wr wr dk# dk don?t care a ba0 d0a d0b d1a d1b d2a d2b d3a d3 figure 2-9. write burst basic sequence: bl=4, rl=4, wl=5, configuration 1 address ck# ck command 012345678 wl = 5 d wr nop wr nop wr nop wr nop wr don?t care dk# dk a ba0 a ba1 a ba0 a ba3 a ba0 d0a d0c d0b d0d d1a d1b d1c d1 remarks 1 . wr : write command a/bap : address a of bank p wl : write latency dpq : data q to bank p 2. any free bank may be used in any given cmd. the sequence shown is only one example of a bank sequence. 24 data sheet m18814ej4v0ds pd48288118 figure 2-10. write followed by read: bl=2, rl=4, wl=5, configuration 1 ck# ck command 012 34567 89 address wl = 5 rl = 4 d q1a q2a q1b d0a d0b wr rd rd nop nop nop nop nop nop nop dont care qkx qkx# dk# dk q a ba0 a ba2 a ba1 undefined q2b figure 2-11. write followed by read: bl=4, rl=4, wl=5, configuration 1 ck# ck command 012 34567 89 address wl = 5 rl = 4 d wr a ba3 rd wr rd nop nop nop nop nop nop qkx qkx# dk# dk q a ba0 a ba1 a ba2 d0a d0b d0c d0d d2a d2b d2c d2d dont care undefined q1a q1b q1c q1d q3a q3b q3c q3d remark wr : write command rd : read command a/bap : address a of bank p wl : write latency rl : read latency dpq : data q to bank p qpq : data q from bank p 25 data sheet m18814ej4v0ds pd48288118 2.11 read operation (read) read accesses are initiated with a read command, as shown in figure 2-12 . row and bank addresses are provided with the read command. during read bursts, the memory device drives the read data edge-aligned with the qk signal. after a programmable read latency, data is availabl e at the outputs. the data valid signal indicates that valid data will be present in the next half clock cycle. the skew between qk and the crossing point of ck is specified as t ckqk . t qkq0 is the skew between qk0 and the last valid data edge considered the data generated at the q0?q17 in x36 and q0?q8 in x18 data signals. t qkq1 is the skew between qk1 and the last valid data edge considered the data ge nerated at the q18?q35 in x36 and q9?q17 in x18 data signals. t qkqx is derived at each qkx clock edge and is not cumulative over time. t qkq is the maximum of t qkq0 and t qkq1 . after completion of a burst, assuming no other commands hav e been initiated, q will go high-z. back-to-back read commands are possible, producing a continuous flow of output data. minimum read data valid window can be expressed as min.(t qkh , t qkl ) ? 2 x max.(t qkqx ). any read burst may be followed by a subsequent write command. figure 2-16. read followed by write, bl=2, rl=4, wl=5, configuration 1 and figure 2-17. read followed by write, bl=4, rl=4, wl=5, configuration 1 illustrate the timing requirements for a read followed by a write. figure 2-12. read command ck# ck we# ref# cs# address bank address don?t care a ba remark a : address ba : bank address 26 data sheet m18814ej4v0ds pd48288118 figure 2-13. basic read burst timing undefined t qkvld t qkvld t qkq note 1 t qkq t qkq t ckqk qvld q ck# ck qkx qkx# t ckh t ckl t ck t qkl t qkh q1 q0 q2 q3 note 1. minimum read data valid window can be expressed as min.(t qkh , t qkl ) ? 2 x max.(t qkqx ). t ckh and t ckl are recommended to have 50% / 50% duty. remarks 1. t qkq0 is referenced to q0?q8. t qkq1 is referenced to q9?q17. 2. t qkq takes into account the skew between any qkx and any q. 3. t ckqk is specified as ck rising edge to qk rising edge. 27 data sheet m18814ej4v0ds pd48288118 figure 2-14. read burst basic sequence: bl=2, rl=4, configuration 1 ck# ck command 012345678 address q qkx qkx# rd a ba0 a ba1 a ba2 a ba3 a ba0 a ba7 a ba6 a ba5 a ba4 rd rd rd rd rd rd rd rd don?t care undefined qvld rl = 4 q0a q1a q0b q1b q2a q2b q3a q3b q0a figure 2-15. read burst basic sequence: bl=4, rl=4, configuration 1 ck# ck command 012345678 address rl = 4 q qkx qkx# rd a ba0 a ba1 a ba0 a ba1 a ba3 nop rd nop rd nop rd nop rd dont care undefined qvld q0a q0c q0b q0d q1a q1b q1c q1d q0a remark rd : read command a/bap: address a of bank p rl : read latency qpq : data q from bank p 28 data sheet m18814ej4v0ds pd48288118 figure 2-16. read followed by write, bl=2, rl=4, wl=5, configuration 1 ck# ck command 01234567 address rl = 4 d qkx qkx# rd a ba0 a ba1 wr wr nop nop nop nop nop dont care a ba2 wl = 5 dk# dk q d1a d1b d2a d2b undefined q0a q0b figure 2-17. read followed by write, bl=4, rl=4, wl=5, configuration 1 ck# ck command 01234567 address rl = 4 qkx qkx# rd a ba0 a ba2 a ba1 wr rd nop nop nop nop nop don?t care wl = 5 d dk# dk q d1a d1b d1c d1d q0a q0b q0c q0d q2a q2b q2c undefined remark wr : write command rd : read command a/bap : address a of bank p wl : write latency rl : read latency dpq : data q to bank p qpq : data q from bank p 29 data sheet m18814ej4v0ds pd48288118 figure 2-18. read/write interleave: bl=4, t rc =6, wl=7, configuration 2 address ck# ck command 012345678 wl = 7 q rd wr rd wr rd wr rd wr rd qkx# qkx rl = 6 wr d d1a d1c d1b d1d d3a d3b d3c d3d 9 10 t rc = 6 a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba0 a ba1 a ba2 a ba3 12 wr rd wr rd d5c d5b d5a d5d d1a 13 14 a ba5 a ba0 a ba1 a ba2 11 d1 don?t care undefined rd a ba2 q0a q0c q0b q0d q2a q2b q2c q2d q4b q4a q4c q4d q0a q0b q0c q0d q2a figure 2-19. read/write interleave: bl=4, t rc =8, wl=9, configuration 3 789 15 wl = 9 wr rd wr rd wr rd wr rd wr rd wr d1a d1c d1b d1d d3a d3b d3c d3d d5a 16 17 a ba7 a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba6 a ba7 a ba0 a ba1 address ck# ck command 012 q rd wr rd qkx# qkx rl = 8 d t rc = 8 a ba0 a ba1 a ba2 10 11 12 13 14 d5c d5b d5d d7a d7b d7c d7 don?t care undefined q0a q0c q0b q0d q2a q2b q2c q2d q4b q4a q4c q4d q6a q6b q6c q6d q0b q0a q0c remark wr : write command rd : read command a/bap: address a of bank p wl : write latency rl : read latency dpq : data q to bank p qpq : data q from bank p 30 data sheet m18814ej4v0ds pd48288118 2.12 refresh operation: auto refresh command (aref) aref is used to perform a refresh cycle on one row in a specific bank. the row addresses are generated by an internal refresh counter; external address balls are ?d on?t care.? the delay between the aref command and a subsequent command to the same bank must be at least t rc . within a period of 32 ms (t ref ), the entire memory must be refreshed. figure 2-21. illustrates an example of a continuous refresh sequence. other refresh strategies, su ch as burst refresh, are also possible. figure 2-20. auto refresh command ck# ck we# ref# cs# address bank address ba don?t care remark ba: bank address figure 2-21. auto refresh cycle ck# ck command t rc arf x ac y ac x ac y don?t care remarks 1 . acx: any command on bank x arfx: auto refresh bank x acy: any command on different bank. 2 . t rc is configuration-dependent. refer to table 2-4. configuration table . 31 data sheet m18814ej4v0ds pd48288118 2.13 on-die termination on-die termination (odt) is enabled by setting a9 to ?1? during an mrs command. with odt on, all the dqs and dm are terminated to v tt with a resistance r tt . the command, address, and clock signals are not terminated. figure 2-22. below shows the equivalent circuit of a q receiver with odt. odts are dynamically switched off during read commands and are designed to be off prior to the pd48288118 driving the bus. similarly, odts are designed to switch on after the pd48288118 has issued the last piece of data. odt at the d inputs and dm are always on. table 2-5. on-die termination dc parameters description symbol min. max. units note termination voltage v tt 0.95 x v ref 1.05 x v ref v 1,2 on-die termination r tt 125 185 3 notes 1. all voltages referenced to v ss (gnd). 2. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. the r tt value is measured at 95c t c. figure 2-22. on- die termination-equivalent circuit v tt r tt sw receiver q figure 2-23. read burst with odt: bl=2, configuration 1 ck# ck command 012345678 address rl = 4 q qkx qkx# rd a ba0 a ba1 a ba2 rd rd nop nop nop nop nop nop don?t care undefined odt odt on qvld odt off odt on q0a q1a q0b q1b q2a q2b remark rd : read command a/bap: address a of bank p rl : read latency qpq : data q from bank p 32 data sheet m18814ej4v0ds pd48288118 figure 2-24. read nop read with odt: bl=2, configuration 1 ck# ck command 012345678 address rl = 4 q qkx qkx# q0a q0b q2a q2b rd a ba0 a ba2 nop rd nop nop nop nop nop nop don?t care undefined odt odt on qvld odt on odt off odt off odt on figure 2-25. read nop nop read with odt: bl=2, configuration 1 ck# ck command 012345678 address rl = 4 q qkx qkx# rd a ba0 a ba2 nop nop rd nop nop nop nop nop don?t care undefined odt odt on qvld odt on odt off odt off odt on 9 q0a q0b q2a q2b remark rd : read command a/bap: address a of bank p rl : read latency qpq : data q from bank p 33 data sheet m18814ej4v0ds pd48288118 2.14 operation with multiplexed address in multiplexed address mode, the address can be provided to the pd48288118 in two parts that are latched into the memory with two consecutive rising clock edges. this prov ides the advantage that a ma ximum of 11 address balls are required to control the pd48288118, reducing the number of balls on the controller side. the data bus efficiency in continuous burst mode is not affected for bl=4 and bl=8 sinc e at least two clocks are required to read the data out of the memory. the bank addresses are delivered to the pd48288118 at the same time as the write command and the first address part, ax. this option is available by setting bit a5 to ?1? in the m ode register. once this bit is set, the read, write, and mrs commands follow the format described in figure 2-26 . see figure 2-28. power-up sequence in multiplexed address mode for the power-up sequence. figure 2-26. command description in multiplexed ck# ck we# ref# cs# address bank address read write don?t care mrs ax ay ay ax ay ax ba ba remarks 1. ax, ay: address ba : bank address 2. the minimum setup and hold times of the two address parts are defined t as and t ah . 34 data sheet m18814ej4v0ds pd48288118 figure 2-27. mode register set command in multiplexed address mode a4 a5 a4 a3 a3 a0 a8 a9 a3x 0 1 bl 4 a4x 0 1 8 note 2 0 0 1 1 a9 a9y 0 1 a8 a4y a3y a0x 10 configuration configuration configuration 1 note 2 (default) reserved reserved reserved 1 note 2 not valid 2 (default) pll enabled pll reset pll reset burst length burst length pll reset address mux address mux pll reset (default) 2 3 reserved 10 11 01 01 00 00 1 1 0 0 1 0 1 0 11 impedance matching impedance matching a8x 0 1 resistor external a5x 0 1 nonmultiplexed (default) address multiplexed a9x 0 1 enabled termination disabled (default) on-die termination on-die termination unused note 3 (default) ay ax a17 ????? a10 a17 ????? a10 reserved note 1 note 4 notes 1. bits a10?a17 must be set to all ?0?. 2. bl=8 is not available for configuration 1. 3. 30% temperature variation. 4. within 15%. remark the address a0, a3, a4, a5, a8, and a9 must be se t as follows in order to activate the mode register in the multiplexed address mode. figure 2-28. power-up sequence in multiplexed address mode v ext v dd v dd q v ref ck# ck command 200 s min. t mrsc t rc mrs mrs mrs rf0 rf1 rf7 ac address v tt a mrs ax ay t mrsc 1 cycle min. 1 cycle min. nop nop nop nop refresh all banks 15 s a a note 1, 2 note 1, 2 note 2, 3 note 4 don?t care notes 1. recommended all address pins held low during dummy mrs command. 2. a10-a17 must be low. 3. address a5 must be set high (muxed address mode setting when pd48288118 is in normal mode of operation). 4. address a5 must be set high (muxed address mode setting when pd48288118 is already in muxed address mode). remark mrs: mrs command rfp : refresh bank p ac : any command 35 data sheet m18814ej4v0ds pd48288118 2.15 address mapping in multiplexed mode the address mapping is described in table 2-6 as a function of data width and burst length. table 2-6. address mapping in multiplexed address mode data burst ball address width length a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 x18 bl=2 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl=4 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 bl=8 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 x ay x a1 a2 x a6 a7 x a11 a12 a16 a15 remark x means ?don?t care?. 36 data sheet m18814ej4v0ds pd48288118 2.16 read & write configuration in multiplexed address mode in multiplexed address mode, the read and write la tencies are increased by one clock cycle. the pd48288118 cycle time remains the same, as described in table 2-7 . table 2-7. configuration in multiplexed address mode frequency symbol configuration unit 1 note 2 3 t rc 4 6 8 cycles t rl 5 7 9 cycles t wl 6 8 10 cycles 400mhz t rc 20.0 ns t rl 22.5 ns t wl 25.0 ns 300mhz t rc 20.0 26.7 ns t rl 23.3 30.0 ns t wl 26.7 33.3 ns 200mhz t rc 20.0 30.0 40.0 ns t rl 25.0 35.0 45.0 ns t wl 30.0 40.0 50.0 ns note bl=8 is not available for configuration 1. 2.17 refresh command in multiplexed address mode similar to other commands, the refresh command is execut ed on the next rising clock edge when in the multiplexed address mode. however, since only bank address is required for aref, the next command can be applied on the following clock. the operation of the aref command and any other command is represented in figure 2-29 . figure 2-29. burst refresh operation address ck# ck command 012345678 ac aref aref aref aref aref aref aref don?t care aref 9 10 ax ay ac ax ay 11 bank address ba p ba 0 ba 1 ba 2 ba 3 ba 4 ba 5 ba 6 ba7 bap nop remark aref : auto refresh ac : any command ax : first part ax of address ay : second part ay of address bap : bank p is chosen so that t rc is met. 37 data sheet m18814ej4v0ds pd48288118 figure 2-30. write burst basic sequence: bl=4 , with multiplexed addresses, configuration 1 ck# ck command 012 34 567 8 address wl = 6 d wr ax ba0 ay ax ba1 ay ax ba2 ay ax ba3 ay ax ba0 nop wr nop wr nop wr nop wr dk# dk dont care d0a d0b d0c d0d d1a d1 figure 2-31. read burst basic sequence: bl=4, wi th multiplexed addresses, configuration 1, rl=5 undefined ck# ck command 012345678 address rl = 5 q qkx qkx# rd nop rd nop rd dont care ax ba0 qvld rd nop rd nop ax ba1 ay ay ax ba2 ay ax ba0 ay ax ba1 q0a q0c q0b q0d q1a q1b q1c remark wr : write command rd : read command ax/bap : address ax of bank p ay : address ay of bank p dpq : data q to bank p qpq : data q from bank p wl : write latency rl : read latency 38 data sheet m18814ej4v0ds pd48288118 3. jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. table 3-1. test access port (tap) pins pin name pin assignments description tck 12a test clock input. all input are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 11a test mode select. this is the command input for the tap controller state machine. tdi 12v test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 11v test data output. this is the output si de of the serial registers placed between tdi and tdo. output changes in response to the falling edge of tck. remark the device does not have trst (tap reset). the test -logic reset state is entered while tms is held high for five rising edges of tck. the tap cont roller state is also reset on the power-up. table 3-2. jtag dc characteristics (0c t c 95c, 1.7 v v dd 1.9 v, unless otherwise noted) parameter symbol conditions min. max. unit jtag input leakage current i li 0 v v in v dd ? 5.0 +5.0 a jtag i/o leakage current i lo 0 v v in v dd q , ? 5.0 +5.0 a outputs disabled jtag input high voltage v ih v ref + 0.15 v dd + 0.3 v jtag input low voltage v il v ssq ? 0.3 v ref ? 0.15 v jtag output high voltage v oh1 | i ohc | = 100 a v ddq ? 0.2 v v oh2 | i oht | = 2 ma v ddq ? 0.4 v jtag output low voltage v ol1 i olc = 100 a 0.2 v v ol2 i olt = 2 ma 0.4 v note 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 0.7 v for t t ck /2. undershoot: v il (ac) ?0.5 v for t t ck /2. during normal operation, v dd q must not exceed v dd . 39 data sheet m18814ej4v0ds pd48288118 jtag ac test conditions input waveform (rise / fall time 0.3 ns) v ih ( ac ) min. v il ( ac ) max. rise time: 2 v/ns fall time: 2 v/ns v dd q v ss output waveform v dd q / 2 v dd q / 2 test points output load condition 10pf q 50 v tt test point 40 data sheet m18814ej4v0ds pd48288118 table 3-3. jtag ac characteristics (0c t c 95c) parameter symbol conditions min. max. unit note clock clock cycle time t thth 20 ns clock frequency f tf 50 mhz clock high time t thtl 10 ns clock low time t tlth 10 ns output time tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 10 ns setup time tms setup time t mvth 5 ns tdi valid to tck high t dvth 5 ns capture setup time t csj 5 ns 1 hold time tms hold time t thmx 5 ns tck high to tdi invalid t thdx 5 ns capture hold time t chj 5 ns 1 note 1. t csj and t chj refer to the setup and hold time requirements of latching data from the boundary scan register. jtag timing diagram t thth t tlov t tlth t thtl t mvth t thdx t dvth t thmx tck tms tdi tdo t tlox 41 data sheet m18814ej4v0ds pd48288118 table 3-4. scan register definition (1) register name description instruction register the 8 bit instruction registers hold the instructions that are executed by the tap controller. the register can be loaded when it is placed between t he tdi and tdo pins. the instruction register is automatically preloaded with the idcode instructi on at power-up whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to anot her device in the scan chai n with as little delay as possible. the bypass register is set low (v ss ) when the bypass instruction is executed. id register the id register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pi ns when the controller is moved into shift-dr state. boundary register the boundary register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in captur e-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. several tap instructions can be used to activate the boundary register. the scan exit order tables describe which device bump connects to each boundary register location. the first column defines the bit?s posit ion in the boundary register. the second column is the name of the input or i/o at the bump and the third column is the bump number. table 3-5. scan register definition (2) register name bit size unit instruction register 8 bit bypass register 1 bit id register 32 bit boundary register 113 bit table 3-6. id register definition part number organization id [31:28] vendor revision no. id [27:12] part no. id [11:1] vendor id no. id [0] fix bit pd48288118 16m x 18 0001 0001 1000 1010 0111 00000010000 1 42 data sheet m18814ej4v0ds pd48288118 table 3-7. scan exit order bit signal bump bit signal bump bit signal bump no. name id no. name id no. name id 1 dk k1 39 d11 r11 77 d1 c11 2 dk# k2 40 d11 r11 78 d1 c11 3 cs# l2 41 d10 p11 79 q1 c10 4 ref# l1 42 d10 p11 80 q1 c10 5 we# m1 43 q10 p10 81 d0 b11 6 a17 m3 44 q10 p10 82 d0 b11 7 a16 m2 45 d9 n11 83 q0 b10 8 a18 n1 46 d9 n11 84 q0 b10 9 a15 p1 47 q9 n10 85 q4 b3 10 q14 n3 48 q9 n10 86 q4 b3 11 q14 n3 49 dm p12 87 d4 b2 12 d14 n2 50 a19 n12 88 d4 b2 13 d14 n2 51 a11 m11 89 q5 c3 14 q15 p3 52 a12 m10 90 q5 c3 15 q15 p3 53 a10 m12 91 d5 c2 16 d15 p2 54 a13 l12 92 d5 c2 17 d15 p2 55 a14 l11 93 q6 d3 18 qk1 r2 56 ba1 k11 94 q6 d3 19 qk1# r3 57 ck# k12 95 d6 d2 20 d16 t2 58 ck j12 96 d6 d2 21 d16 t2 59 ba0 j11 97 d7 e2 22 q16 t3 60 a4 h11 98 d7 e2 23 q16 t3 61 a3 h12 99 q7 e3 24 d17 u2 62 a0 g12 100 q7 e3 25 d17 u2 63 a2 g10 101 d8 f2 26 q17 u3 64 a1 g11 102 d8 f2 27 q17 u3 65 (a20) e12 103 q8 f3 28 zq v2 66 qvld f12 104 q8 f3 29 q13 u10 67 q3 f10 105 (a21) e1 30 q13 u10 68 q3 f10 106 a5 f1 31 d13 u11 69 d3 f11 107 a6 g2 32 d13 u11 70 d3 f11 108 a7 g3 33 q12 t10 71 q2 e10 109 a8 g1 34 q12 t10 72 q2 e10 110 ba2 h1 35 d12 t11 73 d2 e11 111 a9 h2 36 d12 t11 74 d2 e11 112 nf j2 37 q11 r10 75 qk0 d11 113 nf j1 38 q11 r10 76 qk0# d10 note any unused balls that are in the order will read as a logic ?0?. 43 data sheet m18814ej4v0ds pd48288118 jtag instructions many different instructions (2 8 ) are possible with the 8-bit instruction re gister. all used combinations are listed in table 3-8 , instruction codes. these six instructions are descr ibed in detail below. the remaining instructions are reserved and should not be used. the tap controller used in this ram is fully compliant to t he 1149.1 convention. instructi ons are loaded into the tap controller during the shift-ir state wh en the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the inst ruction register through the tdi and tdo ba lls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. table 3-8 instructions instruction code [7:0] description extest 0000 0000 the extest instruction allows circui try external to the component package to be tested. boundary-scan register cells at output pi ns are used to apply test vectors, while those at input pins capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output drive is turned on and the preload data is driven onto the output pins. idcode 0010 0001 the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instru ction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample / preload 0000 0101 sample / preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads t he data in the rams input and q pins into the boundary scan register. because the ra m clock(s) are independent from the tap clock (tck) it is possible for the tap to a ttempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not har m the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controlle r to shift-dr state then places the boundary scan register between the tdi and tdo pins. clamp 0000 0111 when the clamp instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary scan register. selects the bypass register to be connected between tdi and tdo. data driven by output balls are determined from val ues held in the boundary scan register. high-z 0000 0011 the high-z instruction causes the boundary scan register to be connected between the tdi and tdo. this places all rams outputs into a high-z state. selects the bypass register to be connected between tdi and tdo. all outputs are forced into high impedance state. bypass 1111 1111 when the bypass instruction is loaded in the instruction register, the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. reserved for future use ? the remaining instructions are not implemented but are reserved for future use. do not use these instructions. 44 data sheet m18814ej4v0ds pd48288118 tap controller state diagram test-logic-reset run-test / idle select-dr-scan capture-dr capture-ir shift-dr exit1-dr pause-dr exit2-dr update-dr update-ir exit2-ir pause-ir exit1-ir shift-ir select-ir-scan 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 10 10 11 1 0 1 1 0 1 0 11 45 data sheet m18814ej4v0ds pd48288118 4. package drawing 144-pin tape fbga ( bga) (18.5x11) a a1 a3 a2 1 a b c d e f g h j k l m n p r t u v 2 3 4 5 6 e2 7 8 9 10 11 12 zd ze index mark d d d1 s sd ed se ee y1 s s y s x bab m s wb s wa b a item dimensions d d1 d2 e e1 e2 w a a1 a a3 2 ed ee sd se 18.50 17.90 14.52 2.184 0.08 max. 10.70 0.10 11.00 0.10 1.07 0.10 0.39 0.05 0.51 0.05 0.20 0.15 0.68 1.00 0.80 0.50 2.00 (unit:mm) 0.10 0.20 0.75 1.10 x y y1 zd ze b nec electronics corporation 2008 e e1 4xc0.2 10 d2 index mark a detail of a pa rt p144ff-80-dw1 46 data sheet m18814ej4v0ds pd48288118 5. recommended soldering condition please consult with our sales offices for soldering conditions of these products. types of surface mount devices pd48288118ff-dw1 : 144-pin tape fbga (18.5 x 11) pd48288118ff-dw1-a : 144-pin tape fbga (18.5 x 11) 47 data sheet m18814ej4v0ds pd48288118 6. revision history edition/ page type of location description date this previous re vision (previous edition this edition) edition edition 3rd edition/ throughout throughout modi fication preliminary data sheet data sheet nov. 2008 p45 p45 modification 4. package drawing preliminary information formal information 4th edition/ throughout throughout modification modified terms. jan. 2009 48 data sheet m18814ej4v0ds pd48288118 [memo] 49 data sheet m18814ej4v0ds pd48288118 [memo] 50 data sheet m18814ej4v0ds pd48288118 [memo] 51 data sheet m18814ej4v0ds pd48288118 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 the information in this document is current as of january, 2009. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers mu st incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics pr oduct depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if cu stomers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": |
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